(1) Field of the Invention
The present invention generally relates to a sense amplifier in a semiconductor memory device, and more particularly, to a sense amplifier which detects cell data read out from a memory cell in a semiconductor memory device and amplifies the readout cell data.
(2) Description of the Prior Art
FIG. 1 is a circuit diagram of an SRAM (Static Random Access Memory) having a conventional sense amplifier. A column select signal CS having a high (H) level is applied to bases of transistors Tr3, Tr4 and Tr5 at the same time as word lines WL1 and WL2 are selected. The transistors Tr3-Tr5 are turned ON in response to the column select signal CS, so that bit lines BL and BL are selected and a memory cell 1 connected to both the selected bit lines BL and BL and the selected word lines WL1 and WL2 is activated. The memory cell 1 is comprised of bipolar transistors. A plurality of memory cells 1 are coupled to the bit lines BL and BL. When the memory cell 1 shown in FIG. 1 is selected, the other memory cells connected to the bit lines BL and BL are not selected. In this state, complementary voltage signals (cell data) are read out from the selected (activated) memory cell 1 and transferred to the bit lines BL and BL. In response to the readout cell data, a pre-sense amplifier (also referred to as a first sense amplifier) 2 senses the difference between the potentials of the bit lines BL and BL. The pre-sense amplifier 2 shown in FIG. 1 is a voltage-sense type amplifier and comprises transistors Tr1 and Tr2. When the cell data is such that it increases the bit line BL to the high (H) level and decreases the bit line BL to a low (L) level when read out from the memory cell 1, a collector current of the transistor Tr1 drawn from a final sense amplifier (also referred to as a second sense amplifier) 3 via a readout current signal line (hereafter simply referred to as a read line) RD becomes greater than that of the transistor Tr2 drawn from the second sense amplifier 3 via a read line RD. Transistors Tr21 and Tr22 are connected to the bit lines BL and BL, respectively. An AND logic signal obtained by executing an AND logic operation on a write enable signal WE and a write data signal Din is applied to the base of the transistor Tr21. An AND logic signal obtained by executing an AND logic operation on an inverted version WE of the write enable signal WE and the write data signal Din is applied to the base of the transistor Tr22.
During the above-mentioned cell data readout operation, a fixed reference signal Vref1 is input to bases of input transistors Tr6 and Tr7 of the second sense amplifier 3, so that the transistors Tr6 and Tr7 are activated. When the transistors Tr1 and Tr2 operate in the state where the transistors Tr6 and Tr7 are ON, if the potential of the bit line BL based on the data read out from the selected memory cell 1 is higher than that of the bit line BL, a collector current of the transistor Tr6 becomes greater than that of the transistor Tr7. Thus, a voltage drop developed across a resistor R1 is greater than a voltage drop developed across a resistor R2. Thus, the potential of the base of a transistor Tr8 becomes lower than that of the base of a transistor Tr9. The potentials of the bases of the transistors Tr8 and Tr9 are amplified thereby, so that complementary output signals OUT and OUT are generated. Diodes D1 and D2 which are respectively coupled to the emitters of the transistors TrB and Tr9 serve as level shift diodes which adjust the voltage levels of the complementary output signals OUT and OUT. I1 through I4 are constant-current sources.
In order to increase the data readout speed, it is possible to increase the speed of selecting the bit lines BL and BL. However, in this case, there is a possibility that an unintended bit line pair may be selected at the same time as the true bit line pair is selected or no bit line pair is selected. In such a case, the current input to the final sense amplifier 3 via the read line RD is almost the same as that input thereto via the read line RD. Thus, both the output currents OUT and OUT have intermediate levels. Such intermediate levels cause a malfunction of an ECL (Emitter-Coupled Logic) circuit connected to the output side of the second sense amplifier 3 and/or cause changes in the output levels OUT and OUT although the same cell data as the previously read data is read out.